The present invention relates to a method and apparatus for performing priority control for cells in an ATM (Asynchronous Transfer Mode) switch of an ATM switching system and, more particularly, to a method and apparatus for performing priority control for cells in an output buffer type ATM switch for changing a delay quality class added to each ATM cell to control the ATM cell.
In a conventional ATM switching system, when ATM cells, the number of which exceeds the switching capability of an ATM switch for performing switching between a plurality of input/output lines, are input, an order of cell losses, an order of reading cells temporarily stored in the ATM switch, or the like is set as loss characteristics or delay characteristics in advance, and priority control is performed on the basis of these characteristics (see Japanese Patent Laid-Open No. 4-207543).
FIG. 7 shows a priority control apparatus for cells in a conventional ATM switch. Referring to FIG. 7, reference numerals 71 denote a plurality of cell loss units each of which selectively causes an input cell loss; 72, buffer memories each of which stores a cell output from each cell loss unit 71 in a plurality of areas divided depending on the loss quality classes; 73, buffer amount measuring units each of which measures a buffer use amount in each buffer memory 72; 74, a selector for selecting/outputting a cell from a predetermined one of the buffer memories 72; 75, a loss controller for outputting a cell loss instruction to each cell loss unit 71 on the basis of predetermined loss characteristics; and 76, a delay controller for outputting a cell read instruction to the selector 74 on the basis of predetermined delay characteristics.
An operation related to conventional priority control for cells will be described below. First, a priority class CL(m, n) (where m is a loss quality class, and n is a delay quality class) corresponding to loss characteristics and delay characteristics is added to each cell. A cell loss occurs at a high probability as the loss quality class of the cell is higher, and a cell is delayed at a low probability as the delay quality class of the cell is lower. Input cells are distributed to the cell loss units 71 arranged for respective loss quality classes in accordance with the loss quality classes.
In this case, the loss controller 75 examines a total buffer use amount on the basis of outputs from the buffer amount measuring unit 73, and loss characteristics are referred to on the basis of the buffer use amount to check whether the loss quality class of each input cell is a cell loss class. This determination result is output to a corresponding one of the cell loss units 71. The cell loss unit 71 causes the input cell loss when an output from the loss controller 75 indicates that the input cell loss should occur. When the output from the loss controller 75 indicates that the input cell should be stored, the cell loss unit 71 stores the input cell in one of the divided areas corresponding to the delay quality class of the input cell in the buffer memory 72 corresponding to the loss quality class of the input cell, i.e., a priority class CL(m, n).
In addition, although it is determined that the input cell should be stored, when the buffer memory 72 has no free area, the loss controller 75 instructs the cell loss unit 71 such that the loss of a cell having the lowest class of cells each having a class having a level lower than that of the loss quality class of the stored input cell occur in the buffer memory 72. In this manner, the loss of the cell in the buffer memory 72 occurs, and the input cell is stored in a free area formed by this operation. In this case, when there is no cell having a loss quality class having a level lower than that of the input cell, the input cell loss OCCURS.
The delay controller 76 confirms buffer use amounts in the buffer memories 72 on the basis outputs from the buffer amount measuring units in accordance with a predetermined read timing and instructs the selector 74 to read designated cells each having a lower delay quality class from the buffer memories in which cells are stored. The selector 74 reads cells from the buffer memory 72 designed by the delay controller 76 and outputs cells as output cells from the output terminal of the selector 74.
In the above conventional method and apparatus for performing priority control for cells in an ATM switch, however, a quality class consisting of a loss quality class and a delay quality class is fixedly added to each of-input cells to determine the priority of the input cells, and cells are always read starting from a cell having a higher priority. For this reason, when an excessive traffic is spontaneously (burst) input in each buffer memory having a delay quality class to generate congestion, and a satisfactory delay quality may not be obtained, reading is always started from a cell having a higher delay quality, and the congestion cannot be properly avoided. Therefore, the method and apparatus for performing priority control for cells has a low resistance to such a spontaneous excessive traffic.